Printed circuit board and method of manufacturing printed circuit board

ABSTRACT

Disclosed herein is a printed circuit board including a base substrate, a photosensitive insulating layer formed on an upper portion of the base substrate, and a circuit pattern formed to be buried within the photosensitive insulating film.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2012-0085307, filed on Aug. 3, 2012, entitled “Printed Circuit Boardand Method of Manufacturing a Printed Circuit Board”, which is herebyincorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a printed circuit board and a method ofmanufacturing a printed circuit board.

2. Description of the Related Art

Recently, a demand for a technique of directly mounting semiconductorchips on a printed circuit board (PCB) to cope with high density ofsemiconductor chips and a high speed of signal transmission isincreasing, and in line with this, the development of a PCB having highdensity and high reliability to cope with the high density ofsemiconductor chips is required.

Requirements for a PCB having high density and high reliability areclosely related to specifications of a semiconductor chip, and obtainingfiner circuits, a high level of electrical characteristics, a high speedsignal transmission structure, high reliability, high functionality, andthe like, are on the issue to be tackled. In order to address theseproblems, a PCB technique allowing for a formation of micro-via holes isrequired (U.S. Pat. No. 6,240,636).

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide a printedcircuit board and a method of manufacturing a printed circuit boardcapable of forming a plurality of via holes by using exposure anddevelopment without increasing a process time and cost.

The present invention has also been made in an effort to provide aprinted circuit board and a method of manufacturing a printed circuitboard capable of simultaneously forming a via and a circuit pattern tothus reduce a process time.

The present invention has also been made in an effort to provide aprinted circuit board and a method of manufacturing a printed circuitboard capable of increasing a degree of freedom in designing a circuitpattern.

The present invention has also been made in an effort to provide aprinted circuit board and a method of manufacturing a printed circuitboard capable of reducing noise of an electrical signal in electricallyconnecting layers by a circuit pattern and a via formed within aphotosensitive insulating layer.

According to an embodiment of the present invention, there is provided aprinted circuit board including: a base substrate; a photosensitiveinsulating layer formed on an upper portion of the base substrate; and acircuit pattern formed to be buried within the photosensitive insulatingfilm.

The photosensitive insulating layer may include a first photosensitiveinsulating film formed on an upper portion of the base substrate and asecond photosensitive insulating film formed on an upper portion of thefirst photosensitive insulating film.

The first photosensitive insulating film and the second photosensitiveinsulating may have different levels of sensitivity.

The first photosensitive insulating film may have a lower level ofsensitivity than that of the second photosensitive insulating film.

The circuit pattern may include: a first circuit pattern formed on anupper portion of the base substrate and formed to be buried within thefirst photosensitive insulating film; a via lower portion formed on anupper portion of the first circuit pattern; and a second circuit patternformed to be buried within the second photosensitive insulating film andformed on an upper portion of the via lower portion.

The printed circuit pattern may further include a third circuit patternformed on at least one of an upper portion of the second photosensitiveinsulating film, the via upper portion, and an upper portion of thesecond circuit pattern.

The photosensitive insulating layer may further include: a thirdphotosensitive insulating film formed on an upper portion of the secondphotosensitive insulating film and formed to be buried within the thirdcircuit pattern formed on the upper portion of the second photosensitiveinsulating film.

According to another embodiment of the present invention, there isprovided a method of manufacturing a printed circuit board, including:preparing a base substrate having a first circuit pattern formedthereon; forming a photosensitive insulating layer on an upper portionof the base substrate; exposing and developing the photosensitiveinsulating layer to form a first via hole and a second circuit patternhole; and forming a first via and a second circuit pattern in the firstvia hole and the second circuit pattern hole.

In the forming of the photosensitive insulating layer, thephotosensitive insulating layer may include a first photosensitiveinsulating film and a second photosensitive insulating film.

The first photosensitive insulating film and the second photosensitiveinsulating film may have different levels of sensitivity.

The first photosensitive insulating film may have a lower level ofsensitivity than that of the second photosensitive insulating film.

The first photosensitive insulating film and the second photosensitiveinsulating film may be formed as negative photosensitive insulatingfilms.

The forming of the first via hole and the second circuit pattern holemay include: performing an exposing operation on a region other thanregions in which the first via and the second circuit pattern are to beformed on the photosensitive insulating layer; developing the secondphotosensitive insulating film to form the first via hole upper portionand the second circuit pattern hole; performing an exposing operation onthe first photosensitive insulating film exposed through the secondcircuit pattern hole; and developing the first photosensitive insulatingfilm to form a first via hole lower portion.

The first photosensitive insulating film and the second photosensitiveinsulating film may be formed as positive photosensitive insulatingfilms.

The forming of the first via hole and the second circuit pattern holemay include: exposing regions of the second photosensitive insulatingfilm in which the first via and the second circuit pattern are to beformed; developing the exposed second photosensitive insulating film toform the first via hole upper portion and the second circuit patternhole; exposing the first photosensitive insulating film exposed throughthe first via hole upper portion; and developing the exposed firstphotosensitive insulating film to form the first via hole lower portion.

The method may further include: after the forming of the first via andthe second circuit pattern, forming a third circuit pattern on at leastone of an upper portion of the second photosensitive insulating film,the via upper portion, and an upper portion of the second circuitpattern.

The forming of the third circuit pattern may include: forming a platedlayer on an upper portion of the second photosensitive insulating film,the first via upper portion, and an upper portion of the second circuitpattern; forming an etching resist in a region in which the thirdcircuit pattern is to be formed; etching the plated layer exposed by theetching resist; and removing the etching resist.

The plated layer may be formed simultaneously when the first via and thesecond circuit pattern are formed.

The forming of the third circuit pattern may include: forming a platedresist on an upper portion of the second photosensitive insulating filmand having an opening exposing the region in which the third circuitpattern is to be formed; forming the third circuit pattern in theopening of the plated resist; and removing the plated resist.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is an exemplary view illustrating a printed circuit boardaccording to an embodiment of the present invention.

FIGS. 2 through 10 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to an embodiment of thepresent invention.

FIGS. 11 through 19 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to an embodiment of thepresent invention.

FIGS. 20 and 21 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to another embodiment ofthe present invention.

FIGS. 22 and 23 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to another embodiment ofthe present invention.

FIG. 24 is an exemplary view illustrating a printed circuit board havinga multilayer structure according to an embodiment of the presentinvention.

FIG. 25 is an exemplary view illustrating a printed circuit board havinga multilayer structure according to another embodiment of the presentinvention.

FIG. 26 is an exemplary view illustrating a printed circuit board havinga multilayer structure according to another embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The objects, features and advantages of the present invention will bemore clearly understood from the following detailed description of thepreferred embodiments taken in conjunction with the accompanyingdrawings. Throughout the accompanying drawings, the same referencenumerals are used to designate the same or similar components, andredundant descriptions thereof are omitted. Further, in the followingdescription, the terms “first”, “second”, “one side”, “the other side”and the like are used to differentiate a certain component from othercomponents, but the configuration of such components should not beconstrued to be limited by the terms. Further, in the description of thepresent invention, when it is determined that the detailed descriptionof the related art would obscure the gist of the present invention, thedescription thereof will be omitted.

Hereinafter, preferred embodiments of the present invention will bedescribed in detail with reference to the attached drawings.

FIG. 1 is an exemplary view illustrating a printed circuit boardaccording to an embodiment of the present invention.

Referring to FIG. 1, a printed circuit board (PCB) 100 may include abase substrate 110, a first circuit pattern 120, a photosensitiveinsulating layer 130, a first via 170, and a second circuit pattern 160.

The base substrate 110 may be made of a composite polymer resingenerally used as an interlayer insulating material. For example, thePCB may be fabricated to be thinner by employing a pre-preg as the basesubstrate 110. Or, a fine circuit may be easily implemented by employingthe Ajinomoto build up film (ABF) as the base substrate 110. Besides,the base substrate 110 may be made of an epoxy-based resin such as FR-4,BT (Bismaleimide Triazine), or the like, but the present invention isnot particularly limited thereto. Also, a copper clad laminate (CCL) maybe used as the base substrate 110. In an embodiment of the presentinvention, a CCL may be used as the base substrate 110.

The first circuit pattern 120 may be formed on an upper portion of thebase substrate 110. The first circuit pattern 120 may be formed by usinga general circuit pattern forming method. The first circuit pattern 120according to an embodiment of the present invention may be formed bypatterning a copper foil of the CCL as the base substrate 110.

The photosensitive insulating layer 130 may be formed above thesubstrate 110 and the first circuit pattern 120. The photosensitiveinsulating layer 130 may include a first photosensitive insulating film131 and a second photosensitive insulating film 132. The firstphotosensitive insulating film 131 may be formed at an upper portion ofthe base substrate 110 and the first circuit pattern 120. The secondphotosensitive insulating film 132 may be formed on an upper portion ofthe first photosensitive insulating film 131. According to an embodimentof the present invention, the first photosensitive insulating film 131and the second photosensitive insulating film 132 may have differentlevels of sensitivity. For example, the first photosensitive insulatingfilm 131 may be formed to have a lower level of sensitivity than that ofthe second photosensitive insulating film 132.

The first via 170 may be formed on an upper portion of the first circuitpattern 120. The first via 170 may be formed to penetrate thephotosensitive insulating layer 130. Namely, a lower portion of thefirst via 170 may be formed on the first photosensitive insulating film131. Also, an upper portion of the first via 170 may be formed on thesecond photosensitive insulating film 132.

The first via 170 may be made of a conductive material. Namely, thefirst via 170 may be electrically connected to the first circuit pattern120. The first via 170 may be made of the same material as that of thefirst circuit pattern 120.

The second circuit pattern 160 may be formed within the photosensitiveinsulating layer 130. For example, the second circuit pattern 160 may beformed to be buried within the second photosensitive insulating film132. The second circuit pattern 160 may be made of a conductivematerial. Also, the second circuit pattern 160 may be made of the samematerial as that of the first circuit pattern 120 or the first via 170.

FIGS. 2 through 10 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to an embodiment of thepresent invention.

Referring to FIG. 2, the base substrate 110 with the first circuitpattern 120 formed thereon is prepared. The base substrate 110 may bemade of a composite polymer resin generally used as an interlayerinsulating material. For example, the PCB may be fabricated to bethinner by employing a pre-preg as the base substrate 110. Or, a finecircuit may be easily implemented by employing an Ajinomoto build upfilm (ABF) as the base substrate 110. Besides, the base substrate 110may be made of an epoxy-based resin such as FR-4, BT (BismaleimideTriazine), or the like, but the present invention is not particularlylimited thereto. Also, a copper clad laminate (CCL) may be used as thebase substrate 110. In an embodiment of the present invention, a CCL maybe used as the base substrate 110.

The first circuit pattern 120 may be formed on an upper portion of thebase substrate 110. The first circuit pattern 120 may be made of aconductive metal such as copper (Cu), gold (Au), nickel (Ni), or thelike. In an embodiment of the present invention, the first circuitpattern 120 may be formed by patterning a copper foil of a copper cladlaminate (CCL). Although not shown in FIG. 2, a through via may beformed to penetrate the base substrate 110.

Referring to FIG. 3, the photosensitive insulating layer 130 may beformed on an upper portion of the base substrate 110 and the firstcircuit pattern 120. The photosensitive insulating layer 130 may includethe first photosensitive insulating film 131 and the secondphotosensitive insulating film 132.

The first photosensitive insulating film 131 may be attached to thefirst circuit pattern 120 and the base substrate 110. The secondphotosensitive insulating film 132 may be attached to an upper portionof the first photosensitive insulating film 131. Although not shown inFIG. 3, a metal layer (not shown) may be formed on an upper portion ofthe second photosensitive insulating film 132. In this case, after thesecond photosensitive insulating film 132 is formed on an upper portionof the first photosensitive insulating film 131, the metal layer (notshown) may be etched.

The first photosensitive insulating film 131 and the secondphotosensitive insulating film 132 may have different levels ofsensitivity. For example, the first photosensitive insulating film 131may have a lower level of sensitivity than that of the secondphotosensitive insulating film 132. Or, the first photosensitiveinsulating film 131 may have a higher level of sensitivity than that ofthe second photosensitive insulating film 132. The levels of sensitivityof the first photosensitive insulating film 131 and the secondphotosensitive insulating film 132 may be different according to achange in a photo initiator, a filler, and the like. In an embodiment ofthe present invention, the first photosensitive insulating film 131having a lower level of sensitivity than that of the secondphotosensitive insulating film 132 may be used. Also, the firstphotosensitive insulating film 131 and the second photosensitiveinsulating film 132 may be negative photosensitive insulating films.

Since the first photosensitive insulating film 131 and the secondphotosensitive insulating film 132 having different levels ofsensitivity are used, when partial exposure is performed in a follow-upstage, an exposure region may be effectively controlled. For example,when an exposing operation is performed only on the secondphotosensitive insulating film 132, only the second photosensitiveinsulating film 132 may be exposed due to a difference between thelevels of sensitivity of the first photosensitive insulating film 131and the second photosensitive insulating film 132. In this manner, finepatterning may be performed by using the difference between the levelsof sensitivity of the first photosensitive insulating film 131 and thesecond photosensitive insulating film 132 and a quantity of light.

Referring to FIG. 4, a first exposing operation may be performed on thephotosensitive insulating layer 130. During the first exposingoperation, both the first photosensitive insulating film 131 and thesecond photosensitive insulating film 132 may be exposed by adjustingthe amount of exposure. Here, the exposing operation may be performed onthe photosensitive insulating layer 130 excluding portions in which thesecond circuit pattern 160 and the first via 170 are to be formed.

Referring to FIG. 5, a primary developing operation may be performed onthe photosensitive insulating layer 130. By performing the primarydeveloping operation, the second photosensitive insulating film 132 atan upper portion of the first via 170 and a portion in which the secondcircuit pattern 160 is to be formed may be removed. Through the primarydeveloping operation, the first via hole upper portion 142 and a secondcircuit pattern hole 141 may be formed.

Referring to FIG. 6, a secondary exposing operation may be performed onthe photosensitive insulating layer 130. The secondary exposingoperation may be performed on a lower portion of the second circuitpattern hole 141. The secondary exposing operation may be performed onthe non-hardened first photosensitive insulating film 131 positionedunder the second circuit pattern hole 141.

Referring to FIG. 7, a secondary developing operation may be performedon the photosensitive insulating layer 130. As the secondary developingoperation is performed, the first photosensitive insulating film 131 ofa portion which is to become a lower portion of the first via 170 may beremoved. Through such a secondary developing operation, a first via holelower portion 143 may be formed.

By performing exposing and developing operations on the photosensitiveinsulating layer 130 two times according to an embodiment of the presentinvention, a first via hole 144 and a second circuit pattern hole 141may be formed. In this manner, since the via hole is formed by usingexposing and developing operations, a plurality of via holes may beformed without increasing a process time and cost.

Referring to FIG. 8, a seed layer 151 may be formed on thephotosensitive insulating layer 130, the first via hole 144, and thesecond circuit pattern hole 144. The seed layer 151 may be formed toserve as a lead-in wire for electroplating. The seed layer 151 may beformed through a wet plating method such as electroless plating method.Also, the seed layer 151 may be formed through a dry plating method suchas sputtering. The seed layer 151 may be made of a conductive metal suchas copper (Cu), gold (Au), nickel (Ni), or the like.

Referring to FIG. 9, a plated layer 152 may be formed on an upperportion of the seed layer 151. The plated layer 152 may be formedthrough an electroplating method. When electroplating is performed, theinterior of the first via hole 144 and the second circuit pattern hole141 may be filled with the plated layer 152. The plated layer 152 may beformed by using a conductive metal such as copper (Cu), gold (Au),nickel (Ni), or the like.

Referring to FIG. 10, the plated layer 152 and the seed layer 151 formedon the upper portion of the photosensitive insulating layer 130 may beremoved. Here, the plated layer 152 and the seed layer 151 formed on theupper portion of the photosensitive insulating layer 130 may be removedby a general etching method. For example, the plated layer 152 and theseed layer 151 formed on the upper portion of the photosensitiveinsulating layer 130 may be removed by spraying an etching solution.Also, the plated layer 152 and the seed layer 151 formed on the upperportion of the photosensitive insulating layer 130 may be removed bypolishing with a buffer, or the like. As the plated layer 152 and theseed layer 151 at the upper portion of the photosensitive insulatinglayer 130 are removed, the first via 170 and the second circuit pattern160 buried within the photosensitive insulating layer 130 as illustratedin FIG. 10 may be formed.

FIGS. 11 through 19 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to an embodiment of thepresent invention.

Referring to FIG. 11, the base substrate 110 with the first circuitpattern 120 formed thereon is prepared. The base substrate 110 may bemade of a composite polymer resin generally used as an interlayerinsulating material. For example, the PCB may be fabricated to bethinner by employing a pre-preg as the base substrate 110. Or, a finecircuit may be easily implemented by employing an Ajinomoto build upfilm (ABF) as the base substrate 110. Besides, the base substrate 110may be made of an epoxy-based resin such as FR-4, BT (BismaleimideTriazine), or the like, but the present invention is not particularlylimited thereto. Also, a copper clad laminate (CCL) may be used as thebase substrate 110. In an embodiment of the present invention, a CCL maybe used as the base substrate 110.

The first circuit pattern 120 may be formed on an upper portion of thebase substrate 110. The first circuit pattern 120 may be made of aconductive metal such as copper (Cu), gold (Au), nickel (Ni), or thelike. In an embodiment of the present invention, the first circuitpattern 120 may be formed by patterning a copper foil of a copper cladlaminate (CCL). Although not shown in FIG. 11, a through via may beformed to penetrate the base substrate 110.

Referring to FIG. 12, the photosensitive insulating layer 130 may beformed on an upper portion of the substrate 110 and the first circuitpattern 120. The photosensitive insulating layer 130 may include thefirst photosensitive insulating film 131 and the second photosensitiveinsulating film 132.

The first photosensitive insulating film 131 may be attached to thefirst circuit pattern 120 and the base substrate 110. The secondphotosensitive insulating film 132 may be attached to an upper portionof the first photosensitive insulating film 131. Although not shown inFIG. 12, a metal layer (not shown) may be formed on an upper portion ofthe second photosensitive insulating film 132. In this case, after thesecond photosensitive insulating film 132 is formed on an upper portionof the first photosensitive insulating film 131, the metal film (notshown) may be etched to form the second photosensitive insulating layerfilm 132.

The first photosensitive insulating film 131 and the secondphotosensitive insulating film 132 may have different levels ofsensitivity. For example, the first photosensitive insulating film 131may have a lower level of sensitivity than that of the secondphotosensitive insulating film 132. Or, the first photosensitiveinsulating film 131 may have a higher level of sensitivity than that ofthe second photosensitive insulating film 132. The levels of sensitivityof the first photosensitive insulating film 131 and the secondphotosensitive insulating film may be different according to a change ina photoinitiator, a filler, and the like. In an embodiment of thepresent invention, the first photosensitive insulating film 131 having alower level of sensitivity than that of the second photosensitiveinsulating film 132 may be used. Also, the first photosensitiveinsulating film 131 and the second photosensitive insulating film 132may be positive photosensitive insulating films.

Referring to FIG. 13, a first exposing operation may be performed on thephotosensitive insulating layer 130. During the first exposingoperation, only the second photosensitive insulating film 132 may beexposed by adjusting the amount of exposure. Here, the exposingoperation may be performed only on portions in which the second circuitpattern 160 and the first via 170 are to be formed in the secondphotosensitive insulating film 132.

Referring to FIG. 14, a primary developing operation may be performed onthe photosensitive insulating layer 130. By performing the primarydeveloping operation, the second photosensitive insulating film 132 atan upper portion of the first via 170 and a portion in which the secondcircuit pattern 160 is to be formed may be removed. Through the primarydeveloping operation, the first via hole upper portion 142 and a secondcircuit pattern hole 141 may be formed.

Referring to FIG. 15, a secondary exposing operation may be performed onthe photosensitive insulating layer 130. The secondary exposingoperation may be performed on a lower portion of the first via holeupper portion 142. Namely, the secondary exposing operation may beperformed on the first photosensitive insulating film 131 positionedunder the second circuit pattern hole 141.

Referring to FIG. 16, a secondary developing operation may be performedon the photosensitive insulating layer 130. As the secondary developingoperation is performed, the first photosensitive insulating film 131 ofa portion which is to become a lower portion of the first via 170 may beremoved. Through such a secondary developing operation, a first via holelower portion 143 may be formed.

By performing exposing and developing operations on the photosensitiveinsulating layer 130 two times according to an embodiment of the presentinvention, a first via hole 144 and a second circuit pattern hole 141may be formed. In this manner, since the via hole is formed by usingexposing and developing operations, a plurality of via holes may beformed without increasing a process time and cost.

Referring to FIG. 17, a seed layer 151 may be formed on thephotosensitive insulating layer 130, the first via hole 144, and thesecond circuit pattern hole 141. The seed layer 151 may be formed toserve as a lead-in wire for electroplating. The seed layer 151 may beformed through a wet plating method such as electroless plating method.Also, the seed layer 151 may be formed through a dry plating method suchas sputtering. The seed layer 151 may be made of a conductive metal suchas copper (Cu), gold (Au), nickel (Ni), or the like.

Referring to FIG. 18, a plated layer 152 may be formed on the seed layer151. The plated layer 152 may be formed through an electroplatingmethod. When electroplating is performed, the interior of the first viahole 144 and the second circuit pattern hole 141 may be filled with theplated layer 152. The plated layer 152 may be formed by using aconductive metal such as copper (Cu), gold (Au), nickel (Ni), or thelike.

Referring to FIG. 19, the plated layer 152 and the seed layer 151 formedon the upper portion of the photosensitive insulating layer 130 may beremoved. Here, the plated layer 152 and the seed layer 151 formed on theupper portion of the photosensitive insulating layer 130 may be removedby a general etching method. For example, the plated layer 152 and theseed layer 151 formed on the upper portion of the photosensitiveinsulating layer 130 may be removed by spraying an etching solution.Also, the plated layer 152 and the seed layer 151 formed on the upperportion of the photosensitive insulating layer 130 may be removed bypolishing with a buffer, or the like. As the plated layer 152 and theseed layer 151 at the upper portion of the photosensitive insulatinglayer 130 are removed, the first via 170 and the second circuit pattern160 buried within the photosensitive insulating layer 130 as illustratedin FIG. 19 may be formed.

In the case of the PCB and the method of manufacturing a PCB accordingto embodiments of the present invention, noise of an electrical signalcan be reduced when the interlayers are electrically connected by thecircuit pattern and the via formed within the photosensitive insulatinglayer,

FIGS. 20 and 21 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to another embodiment ofthe present invention.

Referring to FIG. 20, an etching resist 210 may be formed on an upperportion of the plated layer 152.

First, the photosensitive insulating layer 130 with the plated layer 152formed thereon and the base substrate 110 may be provided. The firstcircuit pattern 120, the photosensitive insulating layer 130, and theplated layer 152 may be formed on the base substrate 110 according tothe method illustrated in FIGS. 2 through 9. Alternatively, the firstcircuit pattern 120, the photosensitive insulating layer 130, and theplated layer 152 may be formed on the base substrate 110 according tothe method illustrated in FIGS. 11 through 18.

The etching resist 210 may be formed on an upper portion of the platedlayer 152. The etching resist 210 may be formed in a region in which athird circuit pattern 180 is to be formed.

Referring to FIG. 21, the third circuit pattern 180 may be formed onupper portions of the first via 170 and the second circuit pattern 160.An etching operation may be performed on the plated layer 152 with theetching resist 210 formed thereon. Then, the plated layer 152 in regionsother than the region in which the etching resist 210 is formed may beremoved. After the etching operation is performed, the etching resist210 may be removed. In this manner, the third pattern 180 may be formed.Here, the third circuit pattern 180 may be a circuit pattern forelectrically connecting interlayers. Also, the third circuit pattern 180may be a connection pad for an electrical connection with the outside.

Although not shown, a seed layer may be formed under the plated layer152 in FIGS. 20 and 21. Also, the seed layer (not shown) may be removedsimultaneously when the plated layer 152 is etched, or individuallyremoved after the plated layer 152 is etched.

FIGS. 22 and 23 are exemplary views illustrating a method ofmanufacturing a printed circuit board according to another embodiment ofthe present invention.

Referring to FIG. 22, a plated resist 220 may be formed on at least oneof upper portions of the photosensitive insulating layer 130, the firstvia 170, and the second circuit pattern 160.

First, the photosensitive insulating layer 130 with the first circuitpattern 120, the first via 170, and the second circuit pattern 160formed therein and the base substrate 110 may be provided. The firstcircuit pattern 120, the photosensitive insulating layer 130, the firstvia 170, and the second circuit pattern 160 may be formed on the basesubstrate 110 according to the method illustrated in FIGS. 2 through 10.Alternatively, the first circuit pattern 120, the photosensitiveinsulating layer 130, and the plated layer 152 may be formed on the basesubstrate 110 according to the method illustrated in FIGS. 11 through19.

For example, as illustrated in FIG. 22, the plated resist 220 may beformed such that an upper portion of the plated layer 152 in a region inwhich the third circuit pattern 180 is to be formed is exposed.

Referring to FIG. 23, the third circuit pattern 180 may be formed onupper portions of the first via 170 and the second circuit pattern 160.A plating operation may be performed on the portion exposed by theplated resist 220. After the plating operation is performed, the platedresist 220 may be removed. In this manner, the third circuit pattern 180may be formed. Here, the third circuit pattern 180 may be a circuitpattern for electrically connecting interlayers. Also, the third circuitpattern 180 may be a connection pad for an electrical connection withthe outside.

Although not shown, a seed layer may be formed under the plated layer152 in FIGS. 22 and 23. Also, the seed layer (not shown) may be removedsimultaneously when the plated layer 152 is etched, or individuallyremoved after the plated layer 152 is etched.

The third circuit pattern 180 formed thusly is formed on an upperportion of the second circuit pattern 160 and electrically connectedthereto. Namely, the dual circuit patterns may be formed. Thus, althoughthe third circuit pattern 180 is formed to be thin, an electrical signaltransmission function can be enhanced. Also, a degree of freedom ofdesigning the third circuit pattern 180 can be enhanced by the dualstructure of the second circuit pattern 160 and the third circuitpattern 180. Namely, although only a portion of the third circuitpattern 180 is electrically connected to the second circuit pattern 160or the first via 170, an electrical signal transmission function can bemaintained by the second circuit pattern 160. Namely, the shape andposition of the third circuit pattern 180 may be freely selected. Also,the second circuit pattern 160 may be formed to be buried within thephotosensitive insulating layer 130. Thus, the electrical signaltransmission function can be enhanced and the thickness of the PCB canbe reduced.

FIG. 24 is an exemplary view illustrating a printed circuit board havinga multilayer structure according to an embodiment of the presentinvention.

FIGS. 2 through 10 and 11 through 19 illustrate a method of forming aPCB 300 by stacking a single photosensitive insulating layer using twophotosensitive insulating films. Thus, by repeatedly stacking aplurality of photosensitive insulating films 331, 332, 333, and 334 andforming circuit patterns 321, 322, and 323 and vias 324 and 325, the PCB300 having a multilayer structure including the plurality ofphotosensitive insulating layers 330 and 335, the circuit patterns 321,322, and 323, and the vias 324 and 325 may be formed.

FIG. 25 is an exemplary view illustrating a printed circuit board havinga multilayer structure according to another embodiment of the presentinvention.

Referring to FIG. 25, a PCB having a multilayer structure isillustrated.

In the PCB 400 having a multilayer structure according to an embodimentof the present invention, various circuit patterns 421, 422, and 423,and vias 424 and 425 may be formed in two photosensitive insulatinglayers 430 and 435. Namely, the first photosensitive insulating layer430 and the second photosensitive insulating layer 435 may be formed tohave different circuit patterns. As shown in FIG. 25, various types ofcircuit patterns may be configured by exposing and developing thephotosensitive insulating films 431, 432, 433, and 434 constituting thephotosensitive insulating layers 430 and 435, respectively.

FIG. 26 is an exemplary view illustrating a printed circuit board havinga multilayer structure according to another embodiment of the presentinvention.

Referring to FIG. 26, an example of a PCB 500 having a multilayerstructure in which an upper portion and a lower portion of a basesubstrate 510 have different structures is illustrated.

In the PCB 500 having a multilayer structure according to an embodimentof the present invention, a first photosensitive insulating layer 530formed in the upper portion of the base station 510 may include twophotosensitive insulating films 531 and 532. Also, in the PCB 500according to the present embodiment, a second photosensitive insulatinglayer 536 formed in the lower portion of the base station 510 mayinclude three photosensitive insulating films 533, 534, and 535. In thismanner, the different numbers of photosensitive insulating filmsconstituting the first photosensitive insulating layer 530 or the secondphotosensitive insulating layer 536 may be applied. By forming thephotosensitive insulating layers 530 and 536 including the differentnumbers of photosensitive insulating films, various types of circuitpatterns 521, 522, and 523 may be formed as shown in FIG. 26.

According to the PCB and the method of manufacturing a PCB according toembodiments of the present invention, since a via hole is formed byusing exposure and development, a plurality of via holes can be formedwithout increasing a process time and cost. Also, according to the PCBand the method of manufacturing a PCB according to embodiments of thepresent invention, by simultaneously forming a via and a circuitpattern, a process time can be reduced. Also, according to the PCB andthe method of manufacturing a PCB according to embodiments of thepresent invention, noise of an electrical signal can be reduced inelectrically connecting interlayers by the circuit pattern and the viaformed within the photosensitive insulating layer. Also, according tothe PCB and the method of manufacturing a PCB according to embodimentsof the present invention, since a circuit pattern and a via can beformed within and outside a photosensitive insulating layer, a degree offreedom of designing can be increased.

Although the embodiments of the present invention have been disclosedfor illustrative purposes, it will be appreciated that the presentinvention is not limited thereto, and those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the invention.

Accordingly, any and all modifications, variations or equivalentarrangements should be considered to be within the scope of theinvention, and the detailed scope of the invention will be disclosed bythe accompanying claims.

What is claimed is:
 1. A printed circuit board comprising: a basesubstrate; a photosensitive insulating layer formed on an upper portionof the base substrate; and a circuit pattern formed to be buried withinthe photosensitive insulating film.
 2. The printed circuit board as setforth in claim 1, wherein the photosensitive insulating layer includes afirst photosensitive insulating film formed on an upper portion of thebase substrate and a second photosensitive insulating film formed on anupper portion of the first photosensitive insulating film.
 3. Theprinted circuit board as set forth in claim 2, wherein the firstphotosensitive insulating film and the second photosensitive insulatinghave different levels of sensitivity.
 4. The printed circuit board asset forth in claim 2, wherein the first photosensitive insulating filmhas a lower level of sensitivity than that of the second photosensitiveinsulating film.
 5. The printed circuit board as set forth in claim 2,wherein the circuit pattern includes: a first circuit pattern formed onan upper portion of the base substrate and formed to be buried withinthe first photosensitive insulating film; a first via lower portionformed on an upper portion of the first circuit pattern; a secondcircuit pattern formed to be buried within the second photosensitiveinsulating film; and a first via upper portion formed to be buriedwithin the second photosensitive insulating film and formed on an upperportion of the first via lower portion.
 6. The printed circuit board asset forth in claim 5, further comprising: a third circuit pattern formedon at least one of an upper portion of the second photosensitiveinsulating film, the first via upper portion, and an upper portion ofthe second circuit pattern.
 7. The printed circuit board as set forth inclaim 6, wherein the photosensitive insulating layer further includes athird photosensitive insulating film formed on an upper portion of thesecond photosensitive insulating film and formed to be buried within thethird circuit pattern formed on the upper portion of the secondphotosensitive insulating film.
 8. A method of manufacturing a printedcircuit board, the method comprising: preparing a base substrate havinga first circuit pattern formed thereon; forming a photosensitiveinsulating layer on an upper portion of the base substrate; exposing anddeveloping the photosensitive insulating layer to form a first via holeand a second circuit pattern hole; and forming a first via and a secondcircuit pattern in the first via hole and the second circuit patternhole.
 9. The method as set forth in claim 8, wherein in the forming ofthe photosensitive insulating layer, the photosensitive insulating layerincludes a first photosensitive insulating film and a secondphotosensitive insulating film.
 10. The method as set forth in claim 9,wherein the first photosensitive insulating film and the secondphotosensitive insulating film have different levels of sensitivity. 11.The method as set forth in claim 9, wherein the first photosensitiveinsulating film has a lower level of sensitivity than that of the secondphotosensitive insulating film.
 12. The method as set forth in claim 9,wherein the first photosensitive insulating film and the secondphotosensitive insulating film are formed as negative photosensitiveinsulating films.
 13. The method as set forth in claim 12, wherein theforming of the first via hole and the second circuit pattern holeincludes: performing an exposing operation on a region other thanregions in which the first via and the second circuit pattern are to beformed in the photosensitive insulating layer; developing the secondphotosensitive insulating film to form the first via hole upper portionand the second circuit pattern hole; performing an exposing operation onthe first photosensitive insulating film exposed through the secondcircuit pattern hole; and developing the first photosensitive insulatingfilm to form a first via hole lower portion.
 14. The method as set forthin claim 9, wherein the first photosensitive insulating film and thesecond photosensitive insulating film are formed as positivephotosensitive insulating films.
 15. The method as set forth in claim14, wherein the forming of the first via hole and the second circuitpattern hole includes: exposing regions of the second photosensitiveinsulating film in which the first via and the second circuit patternare to be formed; developing the exposed second photosensitiveinsulating film to form the first via hole upper portion and the secondcircuit pattern hole; exposing the first photosensitive insulating filmexposed through the first via hole upper portion; and developing theexposed first photosensitive insulating film to form the first via holelower portion.
 16. The method as set forth in claim 9, furthercomprising: after the forming of the first via and the second circuitpattern, forming a third circuit pattern on at least one of an upperportion of the second photosensitive insulating film, the via upperportion, and an upper portion of the second circuit pattern.
 17. Themethod as set forth in claim 16, wherein the forming of the thirdcircuit pattern includes: forming a plated layer on an upper portion ofthe second photosensitive insulating film, the first via upper portion,and an upper portion of the second circuit pattern; forming an etchingresist in a region in which the third circuit pattern is to be formed;etching the plated layer exposed by the etching resist; and removing theetching resist.
 18. The method as set forth in claim 17, wherein theplated layer is formed simultaneously when the first via and the secondcircuit pattern are formed.
 19. The method as set forth in claim 16,wherein the forming of the third circuit pattern includes: forming aplated resist on an upper portion of the second photosensitiveinsulating film and having an opening exposing the region in which thethird circuit pattern is to be formed; forming the third circuit patternin the opening of the plated resist; and removing the plated resist.